Dr. Hede Ma

hede ma

black ribbon

Professor
Office:
 OCNL 317
Campus Zip: 888 
Phone: (530) 898-4957 
E-mail: hma@csuchico.edu
Ph.D. SUNY Binghamton
Digital and Microprocessor Systems, Fault Tolerance, EMC
Website: http://www.ecst.csuchico.edu/~hma/ 

Education

Ph.D. in Electrical Engineering, 1990
State University of New York - Binghamton
Binghamton, NY 13901, U.S.A.
Doctoral Dissertation Title: Efficient Fault Isolation Schemes for Grey Digital Systems
 

M.S. in Computer Engineering, 1982
Shanghai University of Science and Technology
Shanghai, China
Theses Title: Modeling and Analyzing Packet Switching Networks by Petri Nets

B.S. in Electrical Engineering, Degree Conferral Date: 1980
Shanghai University of Science and Technology
Shanghai, China
Graduation Design Project: Programmable Logic Controller for 125 Ton Press Forging Machine

Experience

Full Professor 2000 - Present
Department of Electrical and Computer Engineering
California State University
Chico, CA 95929-0888

  • Advisor of the student project team that won the first place of IEEE EMC Society’s 2001 Best Student Design, which was an International Competition in electric circuit designs.
  • Teaching Graduate and Undergraduate courses: EECE 615 High-Frequency Design Techniques, EECE 675 Electromagnetic Compatibility, EECE 447 VLSI Design, EECE 643 Computer-Aided Circuit Engineering, EECE 144 Logic Design, EECE 343 Computer Interface Circuits, EECE 311 Linear Circuits, EECE 315 Electronics, etc. using such CAD and CAE software as Altera Quartus II 13.0,  Xilinx UA-ISE-FND, Cadence SPICE, LogicWorks, Logic Aid, Cadence Layout Plus,  programming languages C++, VHDL,  and FPGAs: Altera EPM7160,  EPF10K, FLEX10K, UP1, DE2, etc.
  • Counselor, IEEE CSU, Chico
  • Doing research in areas of Artificial Intelligence, Error Detection and Fault Isolation, Design for Testability, Design for Reliability, Fault-Tolerance, VHDL,  FPGA, and EMC. 

Research Fellow, 2003 - 2004
NASA Jet Propulsion Laboratory
Reliability Engineering, Section 513, Mail Stop 122-107
Pasadena, CA 91109-8099

 Associate Professor, 1995 - 2000
Department of Electrical Engineering
University of Wisconsin
Platteville, WI 53818

Software Engineer, 1998 – 2000
Avista, Inc.
Platteville, WI 53818

  • Did hardware and software testing for the projects of Rockwell Collins GLU/GNLU ILS (Global Landing Unit/Global Navigation Landing Unit Instrument Landing System), Boeing 767, Sundstrand Airbus390.

Architect Engineer, 1997-1998
NewTek, Inc.
8200 1H 10 West #900 
San Antonio, TX 78230

Research/Teaching Assistant
, 1985-1990 
Dept. of Electrical Engineering 
Thomas J. Watson School of Engineering
State University of New York (SUNY) at Binghamton Binghamton, 

NY 13901 Lecturer
, 1983-1984 
College of Computer Science 
Shanghai University 
Shanghai, China

Grants

Grants:

I have developed fifteen proposals to initiate a research program, equip the digital laboratory, and support the student organization, Association of Computer Engineers, since August 22, 2000. The fifteen proposals are all successfully granted to Department of Electrical and Computer Engineering, CSU, Chico, in the amount of $935,506, totally.

  • Constructing Mathematical Models for Stochastic Process of Human Intelligence, Research Foundation of California State University System, $6,252, 2016.
  • LPKF PROTOMAT ® E33 SYSTEM SUITE, SLF CSU, Chico, $11,900, 2016.
  •  Altera Quartus II 8.0 for 75 PCs in the laboratories of ECE department, including updates, valued at $2,995 each per year, for a total equipment grant of $224,625, from Altera, Inc., 2008.
  • 20 Altera UP2 Kits valued at $299 each, for a total equipment grant of  $5,980, from Altera, In., 2008.
  • Xilinx hardware equipment grant (UW-V1000-DK) $244,305  from Xilinx, Inc., 2002.
  • Altera supplementary donation,  MAX+PLUS II Fixed Node Subscriptions of 20 for PC, including updates, valued at $2,000 each per year, for a total equipment grant of $40,000, from Altera, Inc., 2002.
  • Magic XII, Magic 4.0, and DOS Magic for VLSI integrated circuit design and layout, donated by the Software Distribution Office, University of California, Berkeley, 2002.
  • Cadence Pspice A/D ($4,495 each), Capture ($1,495 each), and Layout Plus ($11,495 each), fourteen seats valued at $17,485 each, one Optimizer priced at $3,995, plus the lifetime updates for the fourteen seats ($1,440 per seat for the year of 2001, where Layout Plus $768 per seat, Capture $108 per seat, Pspice A/D $564 per seat), totaling $268,945, from Cadence, Inc., 2001.
  • Altera Design Lab Package (UP 1 Board), five UP 1 boards valued at $695, one PLMJ7000-84 Programming Adapter valued at $375, 50 EPM7032LC44-10 devices valued at $9.80 each, fifteen seats of  MAX+PLUS II Fixed Node Subscriptions for PC, including updates, valued at $2,000 each per year, for a total equipment grant of  $34, 340, from Altera, Inc., 2001.
  • Xilinx UA_ISE_FND ($2,495 each), thirty-four seats valued at $84,830, one US-ISE-FND priced at $2,495, and six DIGILAB-XL-A5 valued at $744, totaling $88,069 from Xilinx, Inc., 2001.
  • Robot Design Project for Association of Computer Engineers, CSU, Chico, $500, Dr. Bill Wattenburg, 2001.
  • Summer Scholarship, $4,000, California State University, 2003.
  • Summer Scholarship, $4,000, California State University, 2001.
  • CELT Small Grant for Instruction, attending EMC Workshop, $300, CSU, Chico, 2000.
  • CELT Small Grant for Instruction, attending COC 2000 Conference, $300, CSU, Chico, 2000. 
  • Integrated Circuit Designs for Artificial Intelligence and Neural Networks, Scholarly Activity Improvement Fund, $3,998, from University of Wisconsin, 1999.
  • Software Engineering improvement, Professional Development Fund, $700, from University of Wisconsin, 1999.
  • A First Step Towards A Software Engineering Program at University of Wisconsin – Platteville, Curriculum Improvement Fund, $3,000, from University of Wisconsin, 1998.
  • Max+Plus II 9.1, $126,000, from Altera, Inc., 1997.
  • Pattern recognition using Boltzmann machine, $7,000, from Oak Ridge National Laboratories Oak Ridge, 1994.
  • Laboratory Equipment Grant, $239,000, from University System of Georgia, 1994. 

Recent Publication

  • H. Ma, “VLSI Test for Electromagnetic Interferences,” 22nd IEEE VLSI Test Symposium, Napa Valley, California, April 25-29, 2004.
  • H. Ma, “CMOS Integrated Circuit Designs with LASI,”  In Proc. 2002 COC National Conference, Myrtle Beach, South Carolina, Nov. 10 – 13, 2002.
  • H. Ma, “Automatic Fault Isolation for reliable Design of Digital Systems,” In Proc. 12th International Conference on Electronics, Communications and Computers, IEEE,  Acapulco, Mexico, Feb. 25 – 28, 2002, pp.116-120.
  • H. Ma, “Gery Digital System Testing,” In Proc. 12th International Conference on Electronics, Communications and Computers, IEEE,  Acapulco, Mexico, Feb. 25 – 28, 2002, pp.105-110.
  • H. Ma, “PCB Design with EMI Mitigation Techniques Using OrCad 9.2 and National Semiconductor’s Web Bench,”  In Proc. 2001 COC National Conference, Myrtle Beach, South Carolina, Nov. 11 – 14, 2001.
  • H. Ma, “Design for Testable Four-Channel Data Transfer Controller Using VHDL,” In Proc. 11th International Conference on Electronics, Communications and Computers, IEEE,  University of Americas- Puebla, Cholula, Puebla, Mexico, Feb. 22 – 24, 2001, pp.129-132.  
  • H. Ma, “Software Test: Theory and Practice,” In Proc. 11th International Conference on Electronics, Communications and Computers, IEEE, University of Americas- Puebla, Cholula, Puebla, Mexico, Feb. 22 – 24, 2001, pp.141-143.
  • H. Ma, “Digital system design using cutting-edge design automation software and field-programmable gate array chips,” In Proc. 2000 COC National Conference, Myrtle Beach, South Carolina, Nov. 12 – 15, 2000, pp.58-62.
  • H. Ma, “Development of a new software Engineering program and curriculum,” The 60th ASEE Midwest Conference, Winona, MN, Oct. 8-10, 1998.
  • H. Ma, “Applications of Design Automation Software for Rapid Prototyping of Digital Systems,” The 60th ASEE Midwest Conference, Winona, MN, Oct. 8-10, 1998.
  • H. Ma, “Bus Expansion Card Design in Microcomputer Architecture and Interfacing,” In Proc. The 59th ASEE Midwest Conference, Iowa City, IA, Oct. 9-11, 1997, pp.111-116.
  • H. Ma, “Engineering Consulting and Engineering Education,” In Proc. The 59th ASEE Midwest Conference, Iowa City, IA, Oct. 9-11, 1997, pp.41-45.
  • H. Ma, “Functions of Final Projects and Project Teams in Computer Engineering Education,” In Proc. The 59th ASEE Midwest Conference, Iowa City, IA, Oct. 9-11, 1997, pp.21-26.
  • H.  Ma, “The Necessity of A New Engineering Course - Patent It Yourself,” In Proc. The ASEE/PSW 1997 Conference, San Luis Obispo, CA, Mar. 14-15, 1997, pp.129-133.
  • H. Ma, "Altera FPGA Applications and Advanced Digital Design," In Proc. The 58th ASEE Midwest Conference, Fargo, ND, Sep. 3-5, 1996, pp.31-37.
  • H. Ma, "Engineering Laboratories and Engineering Education," In Proc. The 58th ASEE Midwest            Conference, Fargo, ND, Sep. 3-5, 1996, pp.51-55.
  • H. Ma, "Pattern recognition using Boltzmann machine," In Proc. IEEE Southeastcon'95, Raleigh, NC,   March           26-29, 1995, pp.23-29.
  • H.  Ma, "A customer-oriented test - estimation test," In Proc. 1994 IEEE Southeastcon'94, Miami, FL., April                11-13, 1994, pp.241-245.
  • H. Ma, "A new testing philosophy - differential test," In Proc. 1993 IEEE Southeastcon'93, Charlotte, NC., April 5-7, 1993, pp.6-9.
  • Y. Liu and H. Ma, "Macrocode for error detection and correction in mass memories," In Proc. 1993 IEEE Southeastcon'93, Charlotte, NC., April 5-7, 1993, pp.201-207.
  • Y. Liu and H. Ma, "A simulation of macrocode for error detection and correction in mass memories," In Proc. 1993 International Simulation Technology Conference , Clear Lake, Texas, Nov. 4-6, 1992, pp.139-144.
  • H. Ma, "An efficient simulator for automatic isolation of intermittent faults in digital systems,"  In Proc. The 40th Computer Simulation Conference, Reno, Nevada, July 27-30, 1992, pp.250-254.
  • Y. Liu and H. D. Ma, "Image analysis using class 2 and class 5A dynamical systems,"  In Proc. The 45th  Conference of The Society for Imaging Science and Technology, East Rutherford, NJ., May 10-15, 1992, pp.201-       204.
  • Y. Liu and H. Ma, "Image analysis using class 3 and class 5B dynamical systems,"  In Proc. The 45th  Conference of The Society for Imaging Science and Technology, East Rutherford, NJ., May 10-15, 1992, pp.205-       208.
  • H. Ma and Y. Liu, "Automatic fault isolation techniques for digital systems,"  In Proc. IEEE Southeastcon'92,                 Birmingham, AL, April 12-15, 1992, pp.335-338.
  • H.  Ma and Y. Liu, "A testable design to test pattern sensitive faults efficiently for semiconductor random access memories,"  In Proc. IEEE Southeastcon'92, Birmingham, AL, April 12-15, 1992, pp.339-342.
  • Y. Liu and H.  Ma, "A comparison of two learning philosophies,"   In Proc. IEEE Southeastcon'92, Birmingham, AL, April 12-15, 1992, pp.247-254.
  • Y. Liu and H.   Ma, "Comparison between image analysis using class 2 and class 3 dynamical systems,"  Image                 Processing Algorithms and techniques III, James R. Sullivan, Editors, Proc. SPIE 1657, 1992, pp.461-475.
  • H.  Ma and Y. Liu, Pattern recognition using w-orbit finite automata," In Proc. Visual Communications and  Image Processing'91: Image processing, Boston, MA, Nov. 11-13, 1991, pp.226-240.
  • H.  Ma and Y. Liu, "Algorithms for moving object pattern recognition using w-orbit finite automata," In Proc. 1991 International Simulation Technology Conference, Orlando, FL, Oct. 21-23, 1991, pp.552-558.
  • Y. Liu and H.  Ma, " Pattern recognition using the third and the fifth classes of dynamical systems," In Proc. The Sixth International Symposium on Methodologies for Intelligent Systems, (Poster Session), Charlotte, NC, Oct. 16-19, 1991, pp.83-94.
  • Y.  Liu and H.  Ma, " A parallel pattern recognition approach," In Proc. The 4th  International Conference on Parallel and Distributed Computing Systems, Washington D.C., Oct. 8-11, 1991, pp.255-260.
  • H.  Ma and Y. Liu, " Efficient placement of error checkers in VLSI systems," In Proc. Test Engineering  Conference, Atlanta, GA, June 25-27, 1991, pp.103-111.
  • H.  Ma and Y.  Liu, "Self-verification of semiconductor random access memories,"  In Proc. Test Engineering  Conference, Atlanta, GA, June 25-27, 1991, pp.113-118.
  • Y. Liu and H.  Ma, " w-orbit finite automata and image compression,"  In Proc. 44th Annual Conference of  the Society for Imaging Science and Technology, St. Paul, Minnesota, May 12-17, 1991, pp.489-492.
  • H.  Ma and Y. Liu, " Functional testing of digital systems described by AHDL," In Proc. 22nd Annual Conference on Modeling and Simulation, Pittsburgh, PA, May 2-3, 1991, pp.1644-1651.
  • H.  Ma and Y. Liu, "Design for diagnosable multipleoutput digital systems,"  In proc. IEEE VLSI Test  Conference, Atlantic City, NJ, April 15-17, 1991, IEEE Computer Press, pp.204-209.
  • Y. Liu and H.  Ma, " w-orbit finite automata for data compression," In Proc. IEEE Data Compression  Conference, Snowbird, Utah, April 8-11, 1991, IEEE Computer Press, pp.166-175.
  • H.  Ma and Y. Liu, "Necessary and sufficient conditions for efficient fault isolation in digital systems,"  In Proc. 25th Annual Conference on Information Sciences and Systems (CISS) 1991, The Johns Hopkins University, Baltimore, MD, March 20-22, 1991, pp.868-873.
  • H.  Ma, Efficient Fault Isolation Schemes for Grey Digital Systems, Ph.D. dissertation, State University of New York, Binghamton, NY, May, 1990.
  • S. Y. H. Su and H. Ma, "Design for Diagnosability and reliability in VLSI systems," In Proc. IEEE  International Test Conference, Washington D. C.,   1988, pp.888-897.
  • S. Y. H. Su and H. Ma, "Fault isolation in grey digital systems,"  In Proc. IEEE International Test Conference, Washington D. C.,   1988, pp.54-63.
  • H. Ma and T. N. Rajshakahara, "A testable design of semiconductor random access memories,"  In Proc. 30th Midwest Conference on Circuits and Systems, Syracuse, NY, 1987, pp.540-543.
  • H. Ma, "Livelock avoidance in packet switching networks,"  In Proc. The Computer Conference of Shanghai, Shanghai, China, 1983.
  • H. Ma, Modeling and Analyzing Packet Switching Network by Petri Nets, M.S. thesis, Shanghai University of Sciences and Technology, Shanghai, China, December, 1982.

Awards and Affiliations

Awards and Honors

  • IEEE Counselor, CSU, Chico, 2003-2015
  • Member, IEEE, 1987-present
  • Member, ACM, 1992-present
  • Member, Sigma Xi Scientific Research Society, 1992 – present
  • Secretary/Treasurer, Sigma Xi Scientific Research Society Savannah Chapter, 1993-94
  • Member, ASEE, 1996 – present
  • Member, IEEE Technical Committee on test engineering, 1990-present
  • Member, IEEE Technical Committee on Software Engineering, 1993-present
  • Chairman, IEEE Student Activities Committee, IEEE Savannah Section, 1992-95
  • Counselor, IEEE Student Chapter, Savannah State University, 1991-95
  • Outstanding Faculty, Dept. of  Engineering, Savannah State University, 1994
  • Referee, IEE Proceedings on Computers and Digital Techniques, 1997 - present
  • Referee, IEEE Transaction on Computer, 1990
  • Judge, Science and Engineering Fair, Savannah, Georgia, 1991-1994
  • Chairman, Student Association of China, State university of  New York at Binghamton, 1986-87
  • Senator, Graduate Student Organization, State University of New York at Binghamton, 1985-86
  • Graduate Scholarship, SUNY at Binghamton, New York, 1985-90
  • Senior Scholarship, Ministry of Education of China, 1984-85
  • Graduate Scholarship, Shanghai University of Sciences and technology, Shanghai, China, 1980-82