Dr. Kurtis Kredo II

Department Chair and Professor

Office:  OCNL 318
Campus Zip: 888 
Phone: (530) 898-4414 
E-mail:  kkredo@csuchico.edu
Ph.D. University of California, Davis
Computer Networks, Computer Architecture

• Education
  • Ph.D. Electrical and Computer Engineering, June 2010 University of California, Davis Advisor: Prasant Mohapatra
  • M.S. Electrical Engineering with Distinction, June 2004 California Polytechnic State University, San Luis Obispo
  • B.S. Computer Engineering Summa Cum Laude, June 2004 California Polytechnic State University, San Luis Obispo
• Experience
  • Associate Professor 2016–Present
    Electrical and Computer Engineering Department California State University, Chico

  • Assistant Professor 2010–2016
    Electrical and Computer Engineering Department California State University, Chico

  • Associate Instructor 2008–2010
    Computer Science Department University of California, Davis
• Research

  Research:

  • FPGA-Based Low-Cost, Real-Time Simulation Systems, 2011 – Present    Low-cost, high-speed simulation of electrical systems using FPGAs. Automated and transparent transformation of graphical models for implementation on FPGAs using source code transformations and High-Level Synthesis.

  
  

  Externally funded by the Office of Naval Research, 2016–2019, for $212,301 and 2019–2022 for $1,146,240. PI: Kurtis Kredo II, co-PI: Roy Crosbie

  • Underwater Acoustic Channel Scheduling and Medium Access Control, 2006 – 2012 Investigation of medium access control protocols for sensor and underwater acoustic networks. Development and evaluation of channel scheduling algorithms and related protocols in underwater wireless networks through network simulation and optimization using integer linear programming. Adaptation to cross-layer issues in underwater wireless networks using a combined scheduling and routing protocol. Evaluation of scheduling granularity and the impact on system performance.

  • Network Co-Processor Design and Development, 2000–2004 Design and development of the third generation CINIC network co-processing card as the hard- ware team leader. Simulation and optimization of system performance. Implementation of FPGA components, including embedded processor peripherals, specialized networking components, and interface logic to system software. Design, layout, and production of prototype subsystems.
• Recent Publications
  • Kredo II, H. Mustafa, R. Crosbie, R. Bednar, and Z. Alavi. "Toward Automated Simulink Model Implementation and Optimization using High-Level Synthesis for FPGAs" IEEE Electric Ship Technologies Symposium (ESTS), Alexandria, VA, USA. August 2019.
  • Mustafa, K. Kredo II, R. Crosbie, R. Bednar, and Z. Alavi. "Real-Time FPGA Simulation of Electric Ship Power System Using High-Level Synthesis" IEEE Electric Ship Technologies Symposium (ESTS), Alexandria, VA, USA. August 2019.
  • K. Kredo II, R. Bednar, R. Crosbie, and J. Zenor. “Techniques for Accelerating Simulations of Electric Ships”, IEEE Electric Ship Technologies Symposium (ESTS), August 2017.
  • K. Kredo II, J. Zenor, R. Bednar, and R. Crosbie. “FPGA-Accelerated Simulink Simulations of Electrical Machines”, IEEE Electric Ship Technologies Symposium (ESTS), June 2015.
  • K. Kredo II. “Automated Feedback and Grading for Computer Architecture Assignments using Web-Based Tools” Journal of Computing Sciences in Colleges, Volume 30, Number 4. April 2015.
  • K. Kredo II and D. Word. “Integration of State-of-the-Art Low Cost Components into Embedded and Digital Systems Design Courses”, ASEE Zone IV Conference, April 2014.
  • R. Crosbie, J. Zenor, R. Bednar, D. Word, K. Kredo II, and N. Hingorani. “Using FPGAs for Low-Cost High-Performance Simulations”, IEEE Electric Ship Technologies Symposium (ESTS), April 2013.
  • K. Kredo II, J. Zenor, J. Yusta, D. Moore, and S. Mish. “Interfacing Techniques for FPGA-based Distributed Simulation”, Grand Challenges in Modelling and Simulation (GCMS), July 2012.
  • K. Kredo II and P. Mohapatra. “Scheduling Granularity in Underwater Acoustic Networks”, ACM International Workshop on UnderWater Networks (WUWNet). December 2011.
  • J. Yusta, J. Zenor, and K. Kredo II. “Efficient High-Speed Ethernet for Real Time Simulation”, Grand Challenges in Modeling and Simulation (GCMS). June 2011.
  • K. Kredo II and P. Mohapatra. “Distributed Scheduling and Routing in Underwater Wireless Networks”, IEEE Global Communications Conference (GlobeCom). December 2010.
  • K. Kredo II, P. Djukic, and P. Mohapatra. “STUMP: Exploiting Position Diversity in the Staggered TDMA Underwater MAC Protocol”, IEEE Conference on Computer Communications (INFOCOM). April 2009
  • K. Kredo II and P. Mohapatra. “A Hybrid Medium Access Control for Underwater Wireless Networks”, ACM International Workshop on Underwater Networks (WUWNet). September 2007.
  • K. Kredo II and P. Mohapatra. “Medium Access Control in Wireless Sensor Networks”, Computer Networks, Volume 51, Issue 4. March 2007.
• Awards and Affiliations

  Awards and Honors

  • Outstanding New Project Investigator 2019, University Office of Research and Sponsored Programs, California State University, Chico
  • GAANN Fellow 2004–2006, University of California, Davis
  • Honors M.S./B.S. Program, California Polytechnic State University, San Luis Obispo, 2002–2004

  Professional Activities

  Member IEEE and ACM

  Invited Talks

  • "Low-Cost High-Speed Simulation of Electrical Machines", CSU, Chico ECC Research Seminar, Feb. 8, 2018.
  • “Communications and Applications.” A three-day seminar covering communications, computer networks, and related applications for professional engineers. Sponsored by Kal Krishnan Consulting Services, Inc. July 18–20, 2013.
  • “Wireless Channel Scheduling with Graph Coloring and Linear Programming.” Department of Mathematics and Statistics Colloquium. April 20, 2012.

  Service

  • Maintain the College of Engineering, Computer Science, and Construction Management Networking and Security Laboratory, a 28-seat lab dedicated to networking and security curriculum. Initial development and organization with Computer Science faculty.Active student and community outreach. Participation in Choose Chico Day (Preview Day) and Admitted Student Preview Day for the Electrical and Computer Engineering Department. Judge for a VEX IQ Challenge Next Level competition series held in Butte  county for local elementary and middle school students. 3D printer demonstration and presentation to Citrus Elementary Students on May 25, 2016. Prepared a demonstration and simple, guided experiment for a visiting Cub Scout Pack on September 14, 2012. Participant on the MESA Graduate School Panel for multiple years. Member of multiple committees at various levels, as outlined below.
    • Council for Promoting Academic Integrity, 2012–Present, University Level
    • Financial Aid Advisory Committee, 2012–2017, University Level
    • University Writing Committee, 2012–Present, University Level
    • Computer Engineering Program Coordinator, 2011–Present, Department Level
    • Computer Engineering Curriculum Committee Chair, 2011–2017, Department Level
    • Electrical and Computer Eng. Personnel Committee, 2016–Present, Department Level
    • Electrical and Computer Eng. Search Committees, 2010–2011, 2013–2014, 2014–2016 (Chair), Department Level